This invention relates to semiconductor memory devices and methods of manufacture thereof, and more particularly to an N-channel silicon gate MOS RAM cell.
Semiconductor memory cells of the one-transistor type are widely used in N-channel silicon gate MOS RAM's as described in U.S. Pat. No. 3,909,631, issued Sept. 30, 1975 to N. Kitagawa, and pending applications Ser. No. 648,594, now abandoned, filed May 3, 1976 by Kitagawa and McAlexander; and Ser. No. 691,735 filed June 1, 1976, now U.S. Pat. No. 4,081,701, by White, McAdams and Redwine, all assigned to Texas Instruments as well as in Electronics, Sept. 13, 1973 at pp. 116-121, Feb. 19, 1976 at pp. 116-121, and May 13, 1976 at pp. 81-86. The most widely manufactured device of this type contains 4096 or 2.sup.12 bits, referred to in the industry as a "4K RAM", or more recently the 16K RAM with 16,384 bits is coming into production. It is expected that 64K and 256K devices will be introduced. The costs in the production of semiconductor devices are such that most of the expense is in bonding, packaging, testing, handling, and the like, rather than the cost of producing the actual circuitry in the small chip of silicon. Thus, any circuit which can be contained within a chip of a given size, for example, 30,000 square mils, will cost about the same as any other. By forming "16K" or 16,384 (2.sup.14) memory cells or bits in a chip, large economies in the cost per bit can result compared to a device containing 4K bits, if reasonable yields are obtained. As the size of a chip increases, the yield decreases, so that at sizes above about 180 mils on a side the advantages are outweighed by reduction in yield. Accordingly, it is desirable to reduce the area occupied by each bit or cell in a RAM. Using photolithographic processes with ultraviolet light and glass masks as is now standard, cell sizes of about one square mil or slightly less are obtained. To produce 64K and 256K RAM's, cell sizes of perhaps 0.2 or 0.3 square mil per bit must be obtained.
One-transistor cells in MOS integrated circuits employ storage capacitors of the type having a silicon oxide dielectric as set forth in U.S. Pat. No. 3,350,760, issued Nov. 7, 1967, to Jack S. Kilby, assigned to Texas Instruments. These may be of the so-called gated type, i.e., voltage dependent, and may have ion implanted regions thereunder as set forth in copending application Ser. No. 645,171, filed Dec. 29, 1975, now abandoned, by Gerald D. Rogers or Ser. No. 722,841, filed Sept. 13, 1976, now U.S. Pat. No. 4,240,092, by C-K Kuo, both assigned to Texas Instruments.
The magnitude of the storage capacitor in a one-transistor cell should be large so that the time between refresh cycles is long, and also so that a good signal is produced in the bit line when a cell is accessed. Large arrays such as 128.times.128 or 256.times.256 mean that the bit lines are long and have high capacitance, reducing the ratio of storage capacitance to bit line capacitance, thus tending to reduce the signal. Also, large arrays dictate small cell area, thus small capacitors. The capacitance can be increased by reducing the oxide dielectric thickness, but this is detrimental to yield. In a dynamic RAM using one-transistor cells, the reliability of the storage capacitor is critical, since the capacitors constitute a major portion of the total thin oxide area of the chip. Generally, reliability and yield of a device are both inversely related to the area of the chip occupied by thin oxide. The capacitor dielectric areas are more critical than the gate areas of the transistors because they are larger and can be under a high electric field stress. Life test data on N-channel MOS dynamic RAM devices shows that 80 to 90% of reliability related failures are due to oxide defects in the storage capacitors. By increasing the capacitor area, the electric field intensity in the storage capacitor dielectric for a given charge stored can be reduced so the reliability is increased. Alternatively, by reducing the field intensity, the oxide can be made thinner for a yield so that the capacitance per unit area may be increased, allowing a reduction in overall thin oxide area.
Increase in capacitance value for a given cell area is accomplished by an anisotropically-etched V-groove as disclosed in copending applications Ser. No. 763,780, filed Jan. 31, 1977 by G. R. Mohan Rao et al, and Ser. No. 765,181, filed Feb. 3, 1977 by G. R. Mohan Rao and C-K Kuo, with assigned to Texas Instruments. The V-groove is also useful in creating a very short channel MOS transistor with accurately controlled threshold voltage by a double ion implant process with anisotropic etch as disclosed in IEEE Journal of Solid State Circuits, February 1977, pp. 3-10.
The principal object of this invention is to provide an improved transistor and storage capacitance combination for a random access memory cell, particularly a very small area cell. Another object is to provide an improved method of making N-channel silicon gate RAM devices. A further object is to provide an MOS RAM cell of smaller size made by a process compatible with existing N-channel silicon gate manufacturing methods.